A Simple VLSI Architecture for Computation of 2-D DCT, Quantization and Zig-zag ordering for JPEG

In this paper, first a comparative simulation study of PSNR is done for two quantization tables, one recommended by JPEG committee and another suitable for hardware simplification. Simulation results indicate that quantization table suitable for hardware simplification can be used for designing JPEG baseline coder circuitry. Then we present a simple finite state machine (FSM) based VLSI architecture and its FPGA implementation from discrete cosine transform (DCT) to zig-zag ordering of transformed coefficients for JPEG baseline coder. 1-D DCT implementation is done for the compressed distributed arithmetic (DA) algorithm reported in previous literature with shifting performed by division operator. Quantizer using only shifter (no adder) and 2-D DCT are combined in single step. Implementation is done on XC2VP30 device on Xilinx Virtex-II Pro FPGA board. Keywords— JPEG, discrete cosine transform (DCT), quantization table, FPGA based design, distributed arithmetic (DA).